Senior Design Verification Engineer
Remote / work from any US location
US Citizen or US Permanent Resident
Full-time/employee + Bonus, Benefits, 401k, Stock Options
Responsibilities:
•Develop and execute verification plans for digital designs using SystemVerilog and UVM
•Create and maintain testbenches, test cases, and test vectors
•Contribute to the development of novel methodologies and verification techniques
•Run simulations to verify design against specifications and analyze results, identify issues, and debug designs
•Implement coverage tracking and metrics
•Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
•Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.
Required Skills & Experience:
•BSEE/MSEE with 5-15 years of hands-on experience in SoC verification using UVM
•Experience in Gate Level Simulation (GLS) setup and process corner failure analysis
•Experience with digital design concepts and ASIC development flow
•Experience writing and debugging RTL using SystemVerilog
•Programming experience using C, C++, and/or Python/Perl
•Ability to work collaboratively across teams and communicate effectively
•Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
•Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects
Preferred Skills:
•Experience verifying RISC-V based systems
•Experience with emulation or FPGA prototyping
•Experience with formal verification methodologies
•Experience with the Chisel hardware description language
•Experience verifying high-speed interfaces such as PCIe and DDR
•Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
DESIGN VERIFICATION GROUP on LinkedIn:
Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
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